CV

Education

• Ph.D. candidate in Department of Computer Science and Engineering, CUHK, Aug. 2022 - July 2026
  • Supervisor: Evangeline FY Young and Martin DF Wong
  • Research Direction: Optimization in the flow of FPGA prototyping (Multi-FPGA partitioning, FPGA placement and routing), Machine Learning in Physical Design
• M.S. Student in Department of Automation, SJTU, Sept. 2019 - Mar. 2022
  • Supervisor: Xiaolin Huang
  • GPA:3.51/4.0 on average
  • Research Direction: Kernel Methods (Random Features), Neural Network Compression (Quantization), Machine Learning
  • Master Thesis: Generalized Construction and Application of Low Dimensional Random Feature Approximation of Kernel Function [paper][slides]
• B.S. Degree in Department of Instrument Science and Engineering, SJTU, Sept. 2015 - Jun. 2019.
  • Rank: 3/55, GPA: 3.80/4.3 on average.
  • Relevant Courses: Machine Learning, Linear Algebra, Caculus, Statistics, C++ Programming and Data Structure, Digital and Analog Circuit
  • Undergraduate Thesis: Performance Improvement Strategy for Mixed Precision Quantized Neural Network [paper]

Publication

• Qin Luo, Xinshi Zang, Qijing Wang, Fangzhou Wang, Evangeline F.Y. Young, Martin D.F. Wong. A Routability-Driven Ultrascale FPGA Macro Placer with Complex Design Constraints. 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2024. [paper]
• Qin Luo, Kun Fang, Jie Yang, Xiaolin Huang. Towards Unbiased Random Features with Lower Variance For Stationary Indefinite Kernels. International Joint Conference on Neural Networks (IJCNN), 2021. [paper][[slides]
• Xinshi Zang, Qin Luo, Zhongwei Shao, Jifeng Zhang, Evangeline F.Y. Young, and Martin D.F. Wong. Dynamic Multi-FPGA Prototyping Platforms with Simultaneous Networking, Placement and Routing. Great Lakes Symposium on VLSI 2024 (GLSVLSI ’24), June 12–14, 2024, Clearwater, FL, USA. [paper]
• Tianshu Chu, Qin Luo, Jie Yang, Xiaolin Huang. Mixed-precision Quantized Neural Networks with Progressively Decreasing Bitwidth. Pattern Recognition (PR), 2021, 111: 107647. [paper]

(Work hard and hope for more good news!!)

Research Project

• FPGA Macro Placement, May. 2023 - Present
  • Analytical Macro placement with machine learning enhancement
  • Third Place in MLCAD2023 contest [Contest Link] and a FCCM short paper.
• Circuit Partition for Multi-FPGA Prototyping, Aug. 2022 - Feb. 2024
  • Timing-driven partitioning, Jan. 2023 - May. 2023
  • Dynamic networking for Multi-FPGA system, Sep. 2022 - Dec. 2022
  • RTL-Hierarchy Guided Multi-FPGA partitioning, Sept. 2023 - Feb. 2024
• Generalized random feature approximation for kernel and its application, Mar. 2020 - Dec. 2021
  • Extended random Fourier features to non-positive definite kernels or non-stationary kernels.
  • Utilized orthogonality to generalized random Fourier features with smaller approximation error and better performance in SVM and SVR tasks.
  • Extensive Research: construction method under memory-constrained conditions and its application in neural network training under a few-shot scenario.
  • Achievement: a paper (IJCNN)
• Mixed precision neural network quantization, Nov. 2018 - Feb. 2020
  • Visualized the separation ability of the feature maps from different classes and utilized the phenomenon to determine the bits of different classes.
  • Conducted classification and object detection experiments to evaluate our proposed mixed precision neural quantization method with evenly quantization methods.
  • Research on regularization and knowledge distillation for quantized neural networks.
  • Achievement: a paper (PR)

Work Experience

• Internship: Megvii Research Shanghai, Dec. 2020 - Jan. 2021
  • Mentor: Yichen Wei, Yuke Zhu
  • Development of action recognition badcase analysis toolkit based on CAM.
  • Research the non-local method and its alternatives to optimize the action recognition model.

Award

• Third Place, MLCAD 2023 contest, FPGA Macro Placement [Certificate] (Lead)
• Third Prize, Simultaneously Dynamic Networking and Circuit Partitioning, Integrated Circuit EDA Elite Challenge, 2022 [Certificate] (Lead)
• Third Place, ISPD 2023 contest, Advanced Security Closure of Physical Layouts [Certificate]
• Second Place, FPGA 2024 contest, Runtime-First FPGA Interchange Routing Contest [Certificate]
• Outstanding Graduate in Shanghai Jiao Tong University, 2019 & 2022.

Service

• Reviewer of Design Automation Conference (DAC), IEEE/ACM International Conference on Computer Aided Design (ICCAD), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Expert Systems With Applications, IEEE Transactions on Neural Networks and Learning Systems (TNNLS)